`timescale 1ns / 1ps `define TRUE 1'b1 `define FALSE 1'b0 module stimulus; wire IZLAZ; reg ULAZ; reg CLOCK, CLEAR; // instanciranje kola ide ovdje initial $monitor ($time, " X = %b Z = %b", ULAZ, IZLAZ); initial begin CLOCK = `FALSE; forever #5 CLOCK = ~CLOCK; end initial // resetovanje kola begin CLEAR = `TRUE; repeat (2) @(negedge CLOCK); CLEAR = `FALSE; end // stimulus initial begin ULAZ = `FALSE; #32 ULAZ = `TRUE; #20 ULAZ = `FALSE; #20 ULAZ = `TRUE; #10 ULAZ = `FALSE; #10 ULAZ = `TRUE; #20 ULAZ = `FALSE; #10 ULAZ = `TRUE; #10 ULAZ = `FALSE; #10 ULAZ = `TRUE; #10 ULAZ = `FALSE; #10 ULAZ = `TRUE; #20 ULAZ = `FALSE; #10 ULAZ = `TRUE; #10 ULAZ = `FALSE; #10 ULAZ = `TRUE; #10 $finish; end endmodule