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PROJEKTOVANJE DIGITALNIH SISTEMA


Semester: 2
ECTS: 6
Status: Obavezan
Lessons: 3+0+1
Double: Ne
ECTS catalogue
Learning outcomes:

After passing the exam, it is expected that the student will be able to: 1. differentiate technologies for implementation of digital circuits; 2. argues reasons for the use of Hardware Description Languages (HDL); 3. describe digital systems modeling domains; 4. describe an architecture of FPGA circuits; 5. describe process of digital system design; 6. differentiate design methodologies „from top to bottom“ and „from bottom to top“; 7. design digital system using Verilog HDL; 8. generate stimulus block for functionality testing of designed digital system; 9. check the behavior of the designed digital system using ISE Design Suite simulator; 10. implement digital system at Xilinx FPGA chip using ISE Design Suite development environment.

Teaching staff

Name Lectures Exercises Laboratory
MILUTIN RADONJIĆ3x1
4P
1x1
4P

Midterm

Termin početka nastave

ECTS catalog

Homeworks

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